Field of the Disclosure
The present disclosure generally relates to the field of a chip package, and more particularly, to a chip package method and a package assembly.
Background of the Disclosure
A package assembly is formed by electrically coupling electrode terminals of a semiconductor die to a leadframe by conductive bumps or bonding wires, and then being encapsulated by a molding process so that leads of the leadframe are exposed from the package body for electric connection with an external circuit.
The leadframe may be preformed and directly used in a package process. However, the preformed leadframe is not flexible for various package wirings. There is a conventional technology in which a leadframe is formed in a package process and compatible with subsequent steps. The conventional approach of forming a leadframe in a package process includes forming a patterned layer as a leadframe, by depositing or electroplating on a package substrate, filling gaps between leads of the leadframe with a molding compound so that individual leads are secured by the molding compound, chemically etching a major portion of the package substrate at its bottom, and then turning upside down the package body and mounting a chip on an opposite surface and drawing out electrode terminals. However, the above approach of forming a leadframe in a package process includes the step of chemically etching the package substrate after forming the leadframe and the step of turning upside down the package body, which introduces difficulty and complexity in the manufacture process and causes poor property of the package assembly.